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FDLY_DO - Fine Delay Digital Output

The DO block handles a digital output signal coming from the connector. This block also adds the capability to delay the output with lower resolution than a normal DO. If the fine delay is disabled, it will behave as a normal DO.

Fields

NameTypeDescription
OCT_DELAYparam uint 7Number of 1/8 ticks to delay (range 0-7)
FINE_DELAYparam uint 511Fine delay (range 0-511)
FINE_DELAY_COMPENSATEDread uint 511Fine delay readout considering voltage/time compensation
INITIAL_ONE_NSread uint 511Initial fine delay readout for a delay of 1ns
VALbit_muxLVDS output value