Skip to article frontmatter Skip to article content

Site not loading correctly?

This may be due to an incorrect BASE_URL configuration. See the MyST Documentation for reference.

Tutorials How-to Guides Explanations Reference

PandABlocks-FPGA Tutorials

Available Blocks

ABSENC - Absolute encoder BITS - Soft inputs and constant bits BIT_TESTER - Pseudo-random Bit Tester CALC - Position Calc CLOCK - Configurable clock COUNTER - Up/Down pulse counter DI - Digital Input DIO - Digital Input/Output DIV - Pulse divider DO - Digital Output EQU - EQU Input EXT_DIO - External direction Digital Input/Output EXT_ST_DIO - External Separately Terminated Digital Input/Output FDLY_DO - Fine Delay Digital Output FILTER - Filter FMC_24V - FMC 24V IO Module FMC_ACQ427 - FMC ACQ427 Module FMC_ACQ430 - FMC ACQ430 Module FMC_LOOPBACK - FMC Loopback Module INENC - Input encoder INENC - Input encoder LUT - 5 Input lookup table LVDSIN - LVDS Input LVDSOUT - LVDS Output OUTENC - Output encoder PCAP - Position Capture PCOMP - Position Compare PGEN - Position Generator PMACENC - Pmac encoder POSENC - Quadrature and step/direction encoder PULSE - One-shot pulse delay and stretch QDEC - Quadrature Decoder SEQ - Sequencer SFP_DLS_EVENTR - SFP Event Receiver Module SFP_LOOPBACK- SFP Loopback Module SFP_PANDA_SYNC - Synchronize data between 2 PandAs SFP_UDPONTRIG - SFP UDP on trig Module SRGATE - Set Reset Gate ST_DIO - Separately Terminated Digital Input/Output SYSTEM - System control FPGA TTLIN - TTL Input TTLOUT - TTL Output

Glossary VHDL style standard Release Notes

TTLIN - TTL Input

The TTLIN block handles the signals from the TTL Input connectors

Fields¶

Name	Type	Description
TERM	param enum	Select TTL input termination
VAL	bit_out	TTL input value

PandABlocks-FPGA

SYSTEM - System control FPGA

PandABlocks-FPGA

TTLOUT - TTL Output