FDLY_DO - Fine Delay Digital Output

The DO block handles a digital output signal coming from the connector. This block also adds the capability to delay the output with lower resolution than a normal DO. If the fine delay is disabled, it will behave as a normal DO.

Fields

Name	Type	Description
OCT_DELAY	param uint 7	Number of 1/8 ticks to delay (range 0-7)
FINE_DELAY	param uint 511	Fine delay (range 0-511)
FINE_DELAY_COMPENSATED	read uint 511	Fine delay readout considering voltage/time compensation
INITIAL_ONE_NS	read uint 511	Initial fine delay readout for a delay of 1ns
VAL	bit_mux	LVDS output value